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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
DESCRIPTION
The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 12 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 22 inputs to 10 outputs. On-chip T/C buffers couple either True (I, B) or Complement (I, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in turn, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLS173 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. Order codes for this device are listed below.
FEATURES
* I/O propagation delay: 30ns (max.) * 12 inputs * 42 AND gates * 10 OR gates * 10 bidirectional I/O lines * Active-High or -Low outputs * 42 product terms:
- 32 logic terms - 10 control terms
PIN CONFIGURATIONS
N Package
I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 I8 9 I9 10 I10 11 GND 12 N = Plastic DIP (300mil-wide) 24 VCC 23 B9 22 B8 21 B7 20 B6 19 B5 18 B4 17 B3 16 B2 15 B1 14 B0 13 I11
* Ni-Cr programmable links * Input loading: -100A (max.) * Power dissipation: 750mW (typ.) * 3-State outputs * TTL compatible
APPLICATIONS
A Package
I3 4 I2 3 I1 2 I0 VCC B9 B8 1 28 27 26 25 NC 24 B7 23 B6 22 B5 21 B4 20 B3 19 NC 12 I9 13 14 15 16 17 18
* Random logic * Code converters * Fault detectors * Function generators * Address mapping * Multiplexing
NC 5 I4 6 I5 7 I6 8 I7 9 I8 10 NC 11
I10 GND I11 B0 B1 B2
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Dual-In-Line 300mil-wide 28-Pin Plastic Leaded Chip Carrier ORDER CODE PLS173N PLS173A DRAWING NUMBER 0410D 0401F
October 22, 1993
25
853-0324 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
LOGIC DIAGRAM
(LOGIC TERMS-P) I0 I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 (CONTROL TERMS)
I9 10 I10 11 I11 13 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 87 0 X0 S8 S7 S6 S5 S4 S3 S2 S1 S0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 23 B9 22 B8 21 B7 20 B6 19 B5 18 B4 17 B3 16 B2 15 B1 14 B0
NOTES: 1. All programmed `AND' gate locations are pulled to logic "1". 2. All programmed `OR' gate locations are pulled to logic "0". 3. Programmable connection.
October 22, 1993
26
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
FUNCTIONAL DIAGRAM
P31 I0 P0 D0 D9
LOGIC FUNCTION
TYPICAL PRODUCT TERM: Pn = A B C D . . . TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = H Z = P0 + P1 + P2 . . . AT OUTPUT POLARITY + L Z = P0 + P1 + P2 + . . .
I11 B0
Z = P0 P1 P2 . . .
B9
NOTES: 1. For each of the 10 outputs, either function Z (Active-High) or Z (Active-Low) is available, but not both. The desired output polarity is programmed via the EX-OR gates. 2. ZX, A, B, C, etc. are user defined connections to fixed inputs (I), and bidirectional pins (B).
S9 X9
B9
S0 X0
B0
ABSOLUTE MAXIMUM RATINGS1
RATING SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating free-air temperature range Storage temperature range 0 -65 -30 Min Max +7 +5.5 +5.5 +30 +100 +75 +150 UNIT VDC VDC VDC mA mA C C
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
The PLS173 is also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Handbook.
NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 22, 1993
27
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
DC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75 VCC 5.25V LIMITS SYMBOL Input VIL VIH VIC Output voltage2 Low High Clamp3 voltage2 VCC = MIN VOL VOH Low4 High5 IOL = 15mA IOH = -2mA 2.4 0.5 V V VCC = MIN VCC = MAX VCC = MIN, IIN = -12mA 2.0 -0.8 -1.2 0.8 V V V PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT
Input current9 VCC = MAX IIL IIH Low High VIN = 0.45V VIN = VCC -100 40 A A
Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 5.5V VOUT = 0.45V IOS ICC Capacitance VCC = 5V IIN CB Input I/O VIN = 2.0V VB = 2.0V 8 15 pF pF Short circuit3, 5, 6 VCC supply current7 VOUT = 0V VCC = MAX -15 150 80 -140 -70 170 mA mA A
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs VIL applied to I11. Pins 1-5 = 0V, Pins 6-10 = 4.5V, Pin 11 = 0V and Pin 13 = 10V. 5. Same conditions as Note 4 except Pin 11 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with I0 and I1 = 0V, and I2 - I11 and B0 - B9 = 4.5V. Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 - I11).
October 22, 1993
28
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
AC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75 VCC 5.25V, R1 = 470, R2 = 1k TEST SYMBOL tPD tOE tOD PARAMETER Propagation delay2 FROM Input Input Input TO Output Output - Output + CONDITION CL = 30pF CL = 30pF CL = 5pF MIN LIMITS TYP 20 20 20 MAX 30 30 30 UNIT ns ns ns
Output enable1 Output disable1
NOTES: 1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORM
+3.0V 90%
TEST LOAD CIRCUIT
VCC 10% +5V S1
0V 5ns +3.0V 90% tR tF 5ns
C1
C2 I0 BY
R1
INPUTS 10% 0V 5ns 5ns
I11 BW
DUT
R2
CL
BX
GND
BZ
OUTPUTS
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
NOTE: C1 and C2 are to bypass VCC to GND.
TIMING DEFINITIONS
SYMBOL tPD tOD PARAMETER Propagation delay between input and output. Delay between input change and when output is off (Hi-Z or High). Delay between input change and when output reflects specified output level.
TIMING DIAGRAM
+3V I, B 1.5V 1.5V 1.5V 0V
VOH B 1.5V VT tOD tOE 1.5V VOL tPD
tOE
October 22, 1993
29
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
LOGIC PROGRAMMING
The PLS173 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP, Data I/O Corporation's ABELTM, and Logical Devices Incorporated's CUPLTM design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLS173 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for addtional information.
OUTPUT POLARITY - (B)
S B X X S B
ACTIVE LEVEL HIGH1 (NON-NVERTING)
CODE H
ACTIVE LEVEL LOW
CODE L
(INVERTING)
AND ARRAY - (I, B)
I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B
P, D STATE INACTIVE1, 2 CODE O STATE I, B
P, D CODE H STATE I, B
P, D CODE L STATE DON'T CARE
P, D CODE -
OR ARRAY - (B)
P S P S
VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs.
Pn STATUS ACTIVE1
CODE A
Pn STATUS INACTIVE
CODE
*
NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn, Dn. 2. Any gate Pn, Dn will be unconditionally inhibited if both the True and Complement of any input (I, B) are left intact.
ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.
October 22, 1993
30
AND ACTIVE B(0) INACTIVE CONTROL HIGH LOW L (POL) H 2. Unused I and B bits in the AND array must be programmed Don't Care (--). 3. Unused product terms can be left blank. A
OR
CUSTOMER NAME
INACTIVE
0
October 22, 1993
NOTES 1. The PLA is shipped with all links intact. Thus a background of entries corresponding to states of virgin links exists in the table. (Shown BLANK for clarity.)
I, B
H
I, B
L
I, B(I)
PHILIPS DEVICE #
PROGRAM TABLE
DON'T CARE
--
PROGRAM TABLE #
T E R M 9 8 7 6 5 4 3 2 1 0 11 15 14 13 12 10
REV
DATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
PIN
VARIABLE NAME
11 10 9
Programmable logic array (22 x 42 x 10)
Philips Semiconductors Programmable Logic Devices
13 11 10
8
9
7
8
7
6 I
6
5
5
4 3
4
3
2
2
1
AND
1
0
31
9 8 7 6 B(I) 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14
9 8 7 6 5 4 3 2 1 0 OR B(0) POLARITY
23 22 21 20 19 18 17 16 15 14
Product specification
PLS173
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array (22 x 42 x 10)
PLS173
SNAP RESOURCE SUMMARY DESIGNATIONS
P31 DIN173 I0 NIN173 P0 D0 D9
I11 B0 DIN173 NIN173
B9 AND CAND TOUT173 S9 X9 OR
B9
S0 B0 X0 EXOR173
October 22, 1993
32

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